![]() ![]() Application granted granted Critical Publication of US6584481B1 publication Critical patent/US6584481B1/en Anticipated expiration legal-status Critical Status Expired - Fee Related legal-status Critical Current Links ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by Xilinx Inc filed Critical Xilinx Inc Priority to US10/215,778 priority Critical patent/US6584481B1/en Assigned to XILINX, INC. ![]() Original Assignee Xilinx Inc Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Miller Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Expired - Fee Related Application number US10/215,778 Inventor Andrew J. Google Patents FPGA implemented bit-serial multiplier and infinite impulse response filterÄownload PDF Info Publication number US6584481B1 US6584481B1 US10/215,778 US21577802A US6584481B1 US 6584481 B1 US6584481 B1 US 6584481B1 US 21577802 A US21577802 A US 21577802A US 6584481 B1 US6584481 B1 US 6584481B1 Authority US United States Prior art keywords bit feedback coupled memory memories Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US6584481B1 - FPGA implemented bit-serial multiplier and infinite impulse response filter ![]() US6584481B1 - FPGA implemented bit-serial multiplier and infinite impulse response filter ![]()
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